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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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CHIPSEL.SA
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1991-03-01
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TTL M68300 BUSINESS CARD COMPUTER CHIP SELECT INIT
OPT P=68332 SETUP FOR 68332 CODE
OPT BRS SHORT BRANCHES PREFERED
******************************************************************************
*** EXPORTED PORTION OF THE MODULE HEADER ***
*V****************************************************************************
******************************************************************************
*** ***
*** MODULE : CHIP SELECT INITIALIZATION ***
*** ***
*** ENVIRONMENT : 68300 Business Card Computer (BCC) Rev. A, B ***
*** For M68300PFB Platform Board, Rev. A, B, C ***
*** ***
*** NOTE: BCC Rev. A + PFB Rev. A = Old System ***
*** BCC Rev. B + PFB Rev. B = New System ***
*** ***
*** PFB Rev. C is jumper selectable to be function- ***
*** ally equivalent to Rev. A or to Rev. B. ***
*** ***
*** ---- DO NOT MIX REV. A's WITH REV. B's! ---- ***
*** ---- NO STACK USAGE (SUBR'S) ALLOWED! ---- ***
*** ***
*** LANGUAGE : 68332 ASSEMBLY LANGUAGE ***
*** ***
*** SUMMARY OF CONTENTS : ***
*** Determines BCC type (A or B) and initializes the appropriate chip ***
*** selects using the corresponding values from the parameter area. ***
*** ***
*** LINK REQUIREMENTS : ***
*** NOTES: ***
*** 1. Source equivalent copy of CPU32Bug parameter area for Motorola ***
*** FREEWARE Bulletin Board System (BBS) to produce object ***
*** equivalent code. See REVISION HISTORY below for version nbr. ***
*** 2. This source code can be freely used at no cost/obligation, ***
*** i.e. it is PUBLIC DOMAIN software. Please report any errors/ ***
*** additions to the SYSOP of the Motorola FREEWARE BBS. ***
*** 3. Parameters which reference linker symbols (XREF/XDEF) will ***
*** not be defined until link time, so the obj. code listed here ***
*** will not match the actual EPROM code. ***
*** ***
******************************************************************************
*^****************************************************************************
*
PAGE
*
******************************************************************************
*** INTERNAL PORTION OF THE MODULE HEADER ***
******************************************************************************
*** ***
*** REVISION HISTORY (add changes to the top): ***
*** ***
*** DATE AUTHOR CHANGES ***
*** ---------- --------------- ------------------------------------- ***
*** 03/01/91 Peter S. Gilmour Compatible with CPU32Bug version 1.00. ***
*** 05/02/90 Peter S. Gilmour Compatible with 332Bug version 1.02. ***
*** 01/17/90 Peter S. Gilmour Initial version port to MS_DOS based ***
*** M68MASM from original source code. ***
*** Compatible with 332Bug version 1.01. ***
******************************************************************************
*** XDEFS : ***
XDEF INIT_CS
*** ***
*** XREFS : ***
XREF PWR_TBL2
XREF .CSBAR0,.CSBAR1,.CSBAR2,.CSBARBT
XREF CSBAR0$
XREF MCR_OR,MCR_AND
XREF SYPCR_OR,SYPCR_AND
*** ***
*** Local macros: ***
*** ***
SYSTEM MACRO ! SETUP MONITOR SPACE
SECTD SET 1 ! DEFINE DATA SECTION
SECTP SET 14 ! DEFINE PROGRAM SECTION
SECTION SECTP ! PUT USER INTO PROG. SECTION
ENDM !
*
* Time delay macro
* - allows bus capacitance to dissipate
* - at least 3 words must be fetched to guarantee dissipation
*
T_DELAY MACRO
NOP
NOP
NOP
ENDM
***
*** Local equates:
***
OLD_BCC EQU 0 Code ID for old BCC
NEW_BCC EQU 1 Code ID for new BCC
*
* For M68300 BCC and PFB.
*
* NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
* addressing (sign extension) can be used.
*
SR_VAL EQU $2700 Status register initial value.
RAM_BASE EQU $0 BCC RAM base address
RAM_SIZE EQU $10000 BCC RAM size (bytes)
ROM1_BASE EQU $E0000 BCC EPROM base address
ROM1_SIZE EQU $20000 BCC EPROM size (bytes)
IRAM_BASE EQU $40000
FPCP_BASE EQU $FFFFE800 PFB MC68881/MC6882 base address
* . (Floating Point Co-Processor)
FCRYSTVAL EQU 32768 Crystal frequency (in Hz)
HI_BASE EQU $FFFFF000 CPU32 module (registers) base high addr
* . This is the default used at power-up!
LO_BASE EQU $007FF000 CPU32 module (registers) base low addr
SIM EQU $A00 CPU32 System Integration Module base addr
RAMCR EQU $B00 CPU32 RAM Control Module base offset
QSM EQU $C00 CPU32 Queued Serial Module base offset
AUTO_BASE EQU $FFFFF800 Autovector base address
* Define bits for Power Up Status (PWRSTATUS) flag:
EXTAL_BIT EQU 31 External Clock flag bit: 0= off (VCO)
CHKSUM_BIT EQU 30 Checksum not pgm'd yet bit: 0= pgm'd
LOCALRAM EQU RAM_BASE base of local RAM
SYSRAMSZ EQU $00004000 size of local RAM (for system use)
LCLRAMMX EQU RAM_SIZE max size of local RAM (for M68332 BCC)
USRRAM EQU LOCALRAM+SYSRAMSZ base of user RAM
USRRAMSZ EQU LCLRAMMX-SYSRAMSZ size of user RAM
RAMSTART EQU LOCALRAM alias for base of local RAM
LOCALROM EQU ROM1_BASE base of local ROM (use PC rel refs!)
LCLROMSZ EQU $00010000 size of local ROM used by 332Bug
ROMUNPGM EQU $FF unprogrammed state of a byte of EPROM
FILL.1 EQU ROMUNPGM fill value for 1 byte = BYTE
FILL.2 EQU FILL.1<<8+FILL.1 fill value for 2 bytes= WORD
FILL.4 EQU FILL.2<<16+FILL.2 fill value for 4 bytes= LONG WORD
RAM2_BASE EQU LOCALRAM+LCLRAMMX Next RAM base address
ROM2_BASE EQU ROM1_BASE+ROM1_SIZE Next ROM base address
VECTSIZ EQU $400 Vector table size
USERLEN EQU $1000 user space reserved
MEMINC EQU $4000 memory increment for 130's or EVM's
STKLEN EQU MEMINC-USERLEN-VECTSIZ-4 size of bug/diag stack + static vars
*
* Interrupt levels & vectors
*
ABORTLVL EQU 7 abort level
ABORTVEC EQU 31 abort vector
ACFAILVL EQU 7 AC-Fail level
ACFAILVC EQU 65 AC-Fail vector
TIMERLVL EQU 6 timer level: M68332 periodic int. timer
TIMERVEC EQU 66 timer vector
*
* Setup Base Addresses:
* 1. A31-A24 must= 0 (MC68332 only uses A0-A23; rest are unused!)
* 2. A10-A0 must= 0 (for Base Address Register usage).
*
ADDRMASK EQU $00FFF800 Address mask (24-bits, A10-A0= 0)
RAM EQU RAM_BASE&ADDRMASK Setup Base Addresses
ROM EQU ROM1_BASE&ADDRMASK Setup Base Addresses
RAM2 EQU RAM2_BASE&ADDRMASK Setup Base Addresses
ROM2 EQU ROM2_BASE&ADDRMASK Setup Base Addresses
FPCP EQU FPCP_BASE&ADDRMASK Setup Base Addresses
IRAM EQU IRAM_BASE&ADDRMASK Setup Base Addresses
AVEC_7 EQU AUTO_BASE&ADDRMASK Setup Base Addresses
CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
CSOR_XX EQU $0000 Reset (unused) value for CSORn
MCR EQU SIM+$00 Module Control Register
MM_BIT EQU 6 . MM bit number in MCR
SYNCR EQU SIM+$04 Clock Synthesizer Control Register
VCO_X EQU $4000 VCO Frequency Control Bit X value
SYPCR EQU SIM+$20 System Protection Control Register
SWE_BIT EQU 7 . SWE bit number in SYPCR
SWP_BIT EQU 6 . SWP bit number in SYPCR
SWE EQU 1<<7 . Software Watchdog Enable in SYPCR
SWP EQU 1<<6 . Software Watchdog Prescale in SYPCR
HME EQU 1<<3 . Halt Monitor Enable in SYPCR
BME EQU 1<<2 . Bus Monitor Enable in SYPCR
BMT8 EQU %11<<0 . Bus Monitor Timing 8 cycles in SYPCR
BMT16 EQU %10<<0 . Bus Monitor Timing 16 cycles in SYPCR
BMT32 EQU %01<<0 . Bus Monitor Timing 32 cycles in SYPCR
BMT64 EQU %00<<0 . Bus Monitor Timing 64 cycles in SYPCR
SWSR EQU SIM+$27 Software Service Reg (WATCHDOG) = BYTE
WATCHV1 EQU $55 . Software Watchdog value #1
WATCHV2 EQU $AA . Software Watchdog value #2
CSPAR EQU SIM+$44 Chip Select Pin Assignment Register
CSBARBT EQU SIM+$48 Chip Select Base Boot Register
CSORBT EQU SIM+$4A Chip Select Option Boot Register
CSBAR0 EQU SIM+$4C Chip Select 0 Base Register
CSOR0 EQU SIM+$4E Chip Select 0 Option Register
CSBAR1 EQU SIM+$50 Chip Select 1 Base Register
CSOR1 EQU SIM+$52 Chip Select 1 Option Register
CSBAR2 EQU SIM+$54 Chip Select 2 Base Register
CSOR2 EQU SIM+$56 Chip Select 2 Option Register
*
* Option Register Equates (CSORBT, CSORn):
*
B2K EQU 0 2K block size
B8K EQU 1 8K block size
B16K EQU 2 16K block size
B64K EQU 3 64K block size
B128K EQU 4 128K block size
B256K EQU 5 256K block size
B512K EQU 6 512K block size
B1M EQU 7 1MB block size
ASYNC EQU $0000 Asynchronous mode
SYNC EQU $8000 Synchronous mode
CS_UPPB EQU 2*$2000 Upper byte
CS_LOWB EQU 1*$2000 Lower byte
CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
CS_R EQU 1*$800 Read
CS_W EQU 2*$800 Write
CS_RW EQU 3*$800 Read or write
CS_AS EQU 0*$400 Address Strobe (AS*)
CS_DS EQU 1*$400 Data Strobe (DS*)
CS_FAST EQU 14 Fast termination DSACK*
CS_EXT EQU 15 External termination DSACK*
CS_WAIT EQU 1*$40 Wait cycles for DSACK*
CS_CSP EQU 0*$10 CPU space
CS_USP EQU 1*$10 User space
CS_SSP EQU 2*$10 Supervisor space
CS_SUSP EQU 3*$10 Supervisor/User space
CS_LVL EQU 1*$2 Interrupt priority level
CS_AVEC EQU 1 Autovector enable
******************************************************************************
*
SYSTEM
* Start Chip Select Initialization:
*
INIT_CS:
MOVE.W #SR_VAL,SR Ensure status register initialized.
LEA HI_BASE,A5 Assume registers are at high memory.
* Set up CSBOOT CHIP SELECT:
* - Long word also gets .CSORBT value into CSORBT register!
* - Must set up wait cycles for Boot ROM before we change Bus Monitor
* timeout value in SYPCR (allows booting in 8-bit mode!).
* - SR and CSBOOT/CSORBT initialized by INIT_T1 routine. See
* INITTBL.SA and RESETV.SA files for details. We repeat the init-
* ialization here in case the user has by-passed/disabled calling
* the INIT_T1 routine via the PWR_TBL1 Power On Branch vector.
*
MOVE.L ((.CSBARBT).L,PC),CSBARBT(A5)
* Set up SYSTEM PROTECTION REGISTER (SYPCR) per paramter area values:
* - controls such things as Software Watchdog, Halt Monitor, Bus Monitor, etc.
* - SYPCR is a write-once register!
MOVE.B SYPCR(A5),D0
MOVEQ.L #0,D7 Clear all flag bits.
BTST #SWP_BIT,D0 Test SWP bit = MODCK* at Power Up
IF <NE> THEN.S If bit set, then
BSET #EXTAL_BIT,D7 . Set External Clock flag bit on.
ENDI
OR.B ((SYPCR_OR).L,PC),D0
AND.B ((SYPCR_AND).L,PC),D0
MOVE.B D0,SYPCR(A5)
* From now on, the Software Watchdog could be running! The SWE_BIT in SYPCR_AND
* controls the Software Watchdog as follows:
* 0 = Watchdog is disabled
* 1 = Watchdog is enabled
* The SWE_BIT in the real SYPCR register can also be tested, but is usually a
* bit more difficult because the module register block is movable!
* Now let's go to 16.7 MHZ:
*
OR.W #VCO_X,SYNCR(A5) X-bit doubles the current speed!
* Set up Module Configuration Register (MCR) per paramter area values:
* - controls such things as FRZBM, MM, IARB, etc.
MOVE.W MCR(A5),D0
OR.W ((MCR_OR).L,PC),D0
AND.W ((MCR_AND).L,PC),D0
MOVE.W D0,MCR(A5)
* From now on, the registers could have been relocated to low memory!
BTST #MM_BIT,D0
IF <EQ> THEN.S If MM bit = 0, then
LEA LO_BASE,A5 . registers are at low memory!
ENDI
* [A5] = register module base address!
* Service the Software Watchdog (just in case it's running!):
MOVE.B #WATCHV1,SWSR(A5)
MOVE.B #WATCHV2,SWSR(A5)
*
* Set up all Chip Selects as "chip selects" in case user's have connected h/w
* devices. Otherwise, address lines would be toggling as program runs and
* possibly cause the devices to be enabled!
MOVE.L #$FFFFFFFF,CSPAR(A5) All = chip selects, 16-bit port
* . (unused bits have no effect!)
* Set up RAM and CSBOOT CHIP SELECTs to old BCC values:
*
MOVE.L ((.CSBAR0).L,PC),CSBAR0(A5)
MOVE.L ((.CSBAR1).L,PC),CSBAR1(A5)
* Test for old BBC by enabling its onboard RAM and ROM.
* If RAM found, then
* assume old BCC with old Platform Board
* else
* assume new BCC with new Platform Board
* endif
* If board == old_BCC
* initialize chip selects for old BCC and old platform board
* else
* initialize chip selects for new BCC and new platform board
* endif
*
* To find RAM:
* ($0000) = $5AA5A55A
* delay to allow bus capacitance to dissipate
* if ($0000) == $5AA5A55A then
* ($0000) = $A55A5AA5
* delay to allow bus capacitance to dissipate
* if ($0000) == $A55A5AA5 then
* RAM found
* endif
* else
* ($2F00) = $5AA5A55A
* delay to allow bus capacitance to dissipate
* if ($2F00) == $5AA5A55A then
* ($2F00) = $A55A5AA5
* delay to allow bus capacitance to dissipate
* if ($2F00) == $A55A5AA5 then
* RAM found
* endif
* endif
* endif
*
* NOTE: By default at Power Up, CSBOOT responds to any address in the
* range of $0-$FFFFF (block size= 1 MB) to select the Boot ROM.
* Since the Boot ROM only uses address lines A0-A16 (128K), it
* appears replicated thru the memory map at every even ROM size
* ($20000) boundary as follows:
* $00000, $20000, $40000, $60000, $80000, $A0000, $C0000, $E0000
* Thus the power up reset vectors for the SP and PC are fetched from
* locations $0-7 and the PC is set to the memory range where we will
* be programming the Boot ROM to appear at via the chip selects.
* When the programming occurs, there are no addressing "glitches"
* because we stay at the same locations!
MOVEQ.L #NEW_BCC,D0
MOVE.L #$5AA5A55A,D1 NOTE: D1 and D2 are inverse patterns!
MOVE.L #$A55A5AA5,D2
SUB.L A0,A0 Test loca. = $0000.
MOVE.L D1,(A0)
T_DELAY
IF.L D1 <EQ> (A0) THEN.S If test loca. is good, then
MOVE.L D2,(A0)
T_DELAY
IF.L D2 <EQ> (A0) THEN.S . If inverse is good, then
MOVEQ.L #OLD_BCC,D0 . Got RAM, so must be old BCC!
ENDI
ELSE.S else maybe just 1 bad loca.
MOVE.W #$2F00,A0 . Test loca. = $2F00.
*------------------------------------------------------------------------------
* CAUTION: In the above "MOVE.W #$XXXX,A0" do not use an address with the
* sign bit set, e.g., $8000, because sign extension will cause a
* BUS ERROR below and crash the system! Also, the address must
* not be in the user ram area ($3000-FFFF), or we could corrupt
* the user's ram! Thus we use $2F00, which is inside CPU32Bug's
* internal stack area.
*------------------------------------------------------------------------------
MOVE.L D1,(A0)
T_DELAY
IF.L D1 <EQ> (A0) THEN.S . If test loca. is good, then
MOVE.L D2,(A0)
T_DELAY
IF.L D2 <EQ> (A0) THEN.S . If inverse is good, then
MOVEQ.L #OLD_BCC,D0 . Got RAM, so must be old BCC.
ENDI
ENDI
ENDI
* Service the Software Watchdog (just in case it's running!):
MOVE.B #WATCHV1,SWSR(A5)
MOVE.B #WATCHV2,SWSR(A5)
CMP.B #OLD_BCC,D0
BNE.S BCC_NEW Branch if old BCC not found!
* Here for old BCC and old Platform board (see Rev. 1 schematics for each):
*
* U1/U3 = 120 nsec RAM w/fast termination
* U2/U4 = ROM, but laid out wrong, so can only be used as 120 nsec RAM!
*
* CSBOOT = BCC U4 332Bug EPROM
* CS0 = BCC U3 read/write enable for MSB=UPPER=EVEN ram
* CS1 = BCC U2 read/write enable for LSB=LOWER=ODD ram
* CS2 = PFB U1/U3 read enable for MSB/LSB=BOTH rams
* CS3 = PFB U1 write enable for LSB=LOWER=ODD ram
* CS4 = PFB U4 read enable for MSB=UPPER=EVEN ram/eprom
* CS5 = PFB U2 read enable for LSB=LOWER=ODD ram/eprom
* CS6 = PFB U5 chip enable for MC68881/882
* CS7 = <unused>
* CS8 = PFB ABORT pushbutton autovector
* CS9 = <unused>
* CS10 = PFB U3 write enable for MSB=UPPER=EVEN ram
* . cut/jump U3-27 from CS4 to CS10 required!
*
* Set up other CHIP SELECT ports (CS0,CS1,CSBOOT already done):
*
BCC_OLD LEA ((.CSBAR2).L,PC),A0 Point to old CS2 entry.
LEA CSBAR2(A5),A1 Point to corresponding SIM reg.
MOVEQ.L #(10-2+1)-1,D0 Set count to do CS2-CS10.
* . ("-1" for DBRA loop below!)
BRA.S CS_COM Go to common init routine!
* Here for new BCC and new Platform board (see Rev. 2 schematics for each):
*
* U1/U3 = 120 nsec RAM w/fast termination
* U2/U4 = 250 nsec ROM (or jumper selectable as RAM)
*
* CSBOOT = BCC U4 CPU32Bug EPROM
* CS0 = BCC U3 write enable for MSB=UPPER=EVEN ram
* CS1 = BCC U2 write enable for LSB=LOWER=ODD ram
* CS2 = BCC U3/U2 read enable for MSB/LSB=BOTH rams
* CS3 = <unused>
* CS4 = PFB ABORT pushbutton autovector
* CS5 = PFB U5 chip enable for MC68881/882
* . cut/jump U5-J3 from CS2 to CS5 required!
* CS6 = PFB U2 read enable for LSB=LOWER=ODD ram/eprom
* CS7 = PFB U4 read enable for MSB=UPPER=EVEN ram/eprom
* CS8 = PFB U1/U3 read enable for MSB/LSB=BOTH rams
* CS9 = PFB U1 write enable for LSB=LOWER=ODD ram
* CS10 = PFB U3 write enable for MSB=UPPER=EVEN ram
*
* Set up all CHIP SELECT ports (CSBOOT already done):
*
BCC_NEW LEA ((CSBAR0$).L,PC),A0 Point to new CS0 entry.
LEA CSBAR0(A5),A1 Point to corresponding SIM reg.
MOVEQ.L #(10-0+1)-1,D0 Set count to do CS0-CS10.
* . ("-1" for DBRA loop below!)
* Common CHIP SELECTS initialization routine:
* A0.L = chip select configuration table entry (base addr)
* A1.L = corresponding SIM register
* D0.W = number of chip selects -1 to be initialized
*
CS_COM MOVE.L (A0)+,(A1)+ Init. SIM base addr + option register.
DBRA D0,CS_COM Continue until all regs init'ed.
* Service the Software Watchdog (just in case it's running!):
MOVE.B #WATCHV1,SWSR(A5)
MOVE.B #WATCHV2,SWSR(A5)
* [D7.L] = Power Up Status Flag
BRA.L PWR_TBL2 Return to Power On Branch Vector
END